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PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1406 is a High Speed, High performance Hysteretic Mode controller. It is part of a two chip solution, with the SC1405 Smart Driver, providing power to advanced micro-processors. It uses a Dynamic Set Point switching technique along with an ultra-fast comparator to provide the control signal to an external high speed Mosfet driver. A 5-bit DAC sets the output voltage, thus providing a voltage resolution of 25mV. SC1406 has two on-chip linear regulators which drive external PNP transistors with output voltage settings of 1.5V and 2.5Vdc. The linear regulator drivers have a separate soft start. A PWRGD TTL level signal is asserted when all voltages are within specifications. The part features Low Battery Detect and Undervoltage Lock-Out for the main Hysteretic controller to assure V-DC is within acceptable limits. An Over-Current comparator disables the main controller during an overcurrent condition using an externally programmable threshold.
FEATURES * * * *
High Speed Hysteretic controller provides high efficiency over a wide operating load range Inherently stable Complete power solution with two LDO drivers (R) Programmable output voltage for Pentium II & III Processors
APPLICATIONS * * *
Laptop and Notebook computers High performance Microprocessor based systems High efficiency distributed power supplies
ORDERING INFORMATION
DEVICE SC1406TS PACKAGE TSSOP-28 TEMP. (T J) 0 - 125C
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
TSSOP-28
Pentium is a registered trademark of Intel Corporation
1
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
PIN DESCRIPTION:
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name HYS CLSET VCOUT VCIN VCBYP VID4 VID3 VID2 VID1 VID0 BASE25 FB25 BASE15 FB15 EN PWRGD LBIN Pin Function Core comparator hysteresis settling. Current limit setting pin. Voltage clamp output. Voltage clamp input. Voltage clamp bypass pin. VID most significant bit input. VID input VID input VID input VID least significant bit input. 2.5V Linear regulator drive. 2.5V Linear regulator output feedback. 1.5V Linear regulator drive. 1.5V Linear regulator output feedback. Enables the IC when high. This is capable of accepting 5.0V signal level. When the main converter output is within +10% of the VID DAC setting, this signal is driven high to VCC level. Internal pull-down 100K. Low battery input. This pin is used to set the minimum voltage to the converter. When the input to this pin is less than 1.225V, the converter is held in an Under-VoltageLock-Out mode regardless of the status of EN. Linear regulators soft start. During power-up, the external soft-start capacitor (1200pF, typ) is charged by an internal 1A current source to set the ramp up time of the linear regulator outputs, 1.5V and 2.5V. This ramp up time is typically 2ms, 6ms max. This is discharged when BIASEN (internal signal) is low. Main controller output soft start. During power-up, the external Soft-Start capacitor (1800pF, typ) is charged by an internal 1A current source to set the ramp up time of the main converter output. This ramp up time is typically 3ms, 6ms max. This is discharged when BIASEN is low. Core soft start current tolerance tracks the LDO soft start current to within 10%. Converter output feedback. VID digital to analog output. Ground Comparator output. Main regulator controller output. Internal pull-down 100K. Supply voltage. Core comparator input pin. Core comparator reference input pin. Current limit input pin. Current limit reference input pin.
18
SSLR
19
SSCORE
20 21 22 23 24 25 26 27 28
CORE DAC GND CO VCC CMP CMPREF CL CLREF
Pentium is a registered trademark of Intel Corporation
2
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
ABSOLUTE MAXIMUM RATINGS
PARAMETER VCC Supply Voltage Low Battery Input Input & Output Pins Enable Operating Junction Temperature Lead Temperature (Soldering) 10 seconds Storage Temperature EN TJ TL TSTG SYMBOL VmaxVCC LBIN MAXIMUM 7 7 VCC + 0.3 GND - 0.3 7 0 to +125 300 -65 to 150 UNITS V V V V C C C
ELECTRICAL CHARACTERISTICS
Unless specified: 0 < TA < 100C; VCC = 3.3V (See Note 1)
PARAMETER SYMBOL CONDITIONS SUPPLY, BIAS, UVLO, VDC MONITOR AND POWERGOOD Supply (VCC, GND) VCC Supply Voltage VCCMAX Range VCC Quiescent Current ICCQ EN is low, 3.0V < VCC < 3.6V EN is high and in UVLO VCC Operating Current ICC EN is high Under Voltage Lock Out Circuit Threshold VHCC Hysteresis Enable Input Input High Input Low Low Battery Monitor Threshold Input Bias Current VTHDC IBDC VLB_IN > VTHDC VLB_IN < VTHDC VCORE Power Good Generator Input Threshold VHCORE VLCORE Output Voltage VHPWRGD (Active Hi) VLPWRGD (Active low) VPWRGD VOUT IPWRGD = 10a (source) EN is high IPWRGD = 10A (sink), EN is high IPWRGD = 10A (sink), UVLO During the latency time (50s) of any VID code change VDAC = 0.9V - 1.675V VLCC VHYSTCC Vih Vil 3.0 < VCC < 5V
MIN
TYP
MAX
UNITS
3.0
3.3
6.0 10 350 15 2.95
V A mA V mV V
10.0
2.7 20 0.7*VCC 0.8 1.175 0.6 1.08*VCC 0.88*VCC 0.95* VCC 0.4 0.8 Don't care 1.225 1.0 1.275 0.3 10.5 1.12*VCC 0.92*VCC
V V A
V V V V V
Note 1: Specification refers to application circuit (Figure 1.).
Pentium is a registered trademark of Intel Corporation
3
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
PARAMETER Core Converter Soft Start Current Core Converter Soft Start Current
SYMBOL CONDITIONS CORE CONVERTER CONTROLLER ISSCORE VSSTERM VSSDIS VVID_IH VVID_IL IVID VDAC_ERR tpdVID_DAC 3.0V < VCC < 3.6V VID (0-4) = 00000...11111 IDAC = 0, VID(0-4) = 00000...11111 Charge (Source) current Discharge (Sink) current
MIN
TYP MAX UNITS
0.6 0.30 1.53
1 1 1.70 150
1.45
A mA
VSSCORE Soft Start Termination Threshold VSSCORE Discharge Threshold VID DAC VID Input Threshold VID Input-Pull-up Current,VID (0-4) Output Voltage Accuracy Settling Time*
1.87 400
V mV V
0.7*VCC 0.8 6 -0.85 40 +0.85 35
A % s
CDAC = 1000pF VID is set to change VCORE from 1.30V to 1.45V or 1.45V to 1.30V CORE Comparator (CMP, CMPREF, HYS, CO) Input Bias Current IBCMP VCPMVCPMREF
VCMP = VCMPREF = 1.3V VCMPREF = 1.3V RHYS = open 1.5
2 3 +2 89 +8 2.5 0.4 +100 +111 +10 +12.5
A mV
Input Offset Voltage Hysteresis Setting Current
ICMPREF Output Voltage VHCO
CMPRHYS = 17k RHYS = 170k Load Impedance = 100k in parallel with 10pF, VCC = 3.0V Load Impedance = 100k in parallel with 10pF, VCC = 3.6V VCMPREF = 1.3V VCMP = +40mV step with +20mV, overdrive TA = 25C, TA = full range VCMPREF = 1.3V VCMP = 40mV step with 20mV overdrive, TA = 25C, TA = full range CCO = 10pF VCC = 3.0V RCO = 100K
A
V V
VLCO
CMP>CMPREF
Propagation Delay Time** Measured at device pins, from the trip point to 50% of CO transition.
Tpd CMP-CO
20 30
ns
20 30 7 10 ns 7 10
Output Rise/Fall Times** Measured between 30% and 70% points of CO transition
TR
TF
Pentium is a registered trademark of Intel Corporation
4
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Current Limit Comparator (CL, CLREF, CLSET) Input Bias Current Current Limit Setting Current *The Tamky device is required to meet the CL setting current requirements for RCLSET of "17k and 170k or "42.5k and 20k". Supplier production testing will use the 17k /170k combination or the 42.5k /20k combination. +ICL |+ICLREF| VCS = 1.3V RCLSET = open VCLREF-VCL = 10mV VCLRER-VCL = -10mV VCLREF-VCL 262.5 = 10mV VCLREF-VCL 175 = -10mV VCLREF-VCL 19.5 = 10mV VCLREF-VCL 13 = -10mV VCLRER-VCL 100.5 = 10mV VCLRER-VCL 67 = -10mV VCLREF-VCL = 10mV VCLRER-VCL = -10mV 222 148 5 7.5 A 5.0 300 200 30 20 120 80 255 170 4 337.5 225 40.5 27 139.5 93 288 192 6 mV A A A A A
RCLSET = 17k
RCLSET = 170k
RCLSET = 42.5k
RCLSET = 20k
Input Offset Voltage Propagation Delay Time** Measured at the device pins, from the trip point to 50% of CO transition
VCL VCLREF Tpd_CL-CO
VCLREF = 1.3V VCMPREF = 1.3V, VCMP = +50mV step with +20mV overdrive, TA = 25C, TA = full range VCMPREF = 1.3V, VCMP = -50mV step with -20mV overdrive, TA = 25C, TA = full range
100 150 ns
100 150
Pentium is a registered trademark of Intel Corporation
5
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
ELECTRICAL CHARACTERISTICS (CONT.)
Unless specified: -0 < TA < 100C; VCC = 3.3V (See test circuit)
PARAMETER 1.5V Linear Regulator Controller Input Bias Current Output Voltage CO_1.5 = 56F, 20m ESR max or 150F, 45m ESR max Capacitance tolerance = 20% Base Drive Output Current 2.5V Linear Regulator Controller Input Bias Current Output Voltage CO_2.5 = 1Fceramic ESR range = 1m - 30m Capacitance tolerance = 20% Base Drive Output Current
SYMBOL
CONDITIONS
MIN TYP MAX UNIT
LINEAR REGULATOR CONTROLLERS ILR15 VO_1.5, Imin = 0.1mA IBASE_1.5
ILR25
VFB_15 = 1.5V IO = 500mA, pnp BJT with BMIN > 50 @ 1.47 1.50 IC = 500mA
1 1.54
mA V
@ 25C VFB_25 = 2.5V IO = Imax, pnp BJT with BMIN > 50 @ IC = 100mA
10
120 1
mA mA V
VO_2.5, Imin = 0A
Imax=0.1A
2.45 2.50
2.55
IBASE_2.5 ILRSS Charge Current, VLRSS = 0V Discharge Current, VLRSS = 1.50V, EN is low or in UVLO
3.5 -0.6 0.3 -1 1 150 1.53 1.70
20 -1.4 1.45 400 1.87
mA A mA mV V
Linear Regulator Soft Start (LRSS) Linear Reg Soft-Start Current
Enable Threshold Soft Start Termination Threshold
VSSLR_EN VTH_LRSS
Voltage Clamp (VCIN, VCOUT, VCBYP) Input Voltage Output Voltage Imin = 10A VH_VCIN VH_VCOUT RVCOUT = 150 tied to VS = 2.5V IVCIN = -10A 0.95 VCIN is open 0.8VS 1.5 1.60 VS V V
VL_VCOUT Progagation Delay** Tpd
VCIN_VCOUT
VVCIN = 0.175V RVCOUT = 150 tied to VS = 2.5V CVCBYP = 1500pF, VCIN steps from 0.175V to 1.50V and back. Measured from 50% of VCIN step to 50% of VCOUT transient
0.375 10 ns
* Guaranteed by design. **Guaranteed by characterization.
Pentium is a registered trademark of Intel Corporation
6
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
VID vs. VDAC VOLTAGE
VID 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MIN 1% < VO 1.658 1.633 1.609 1.584 1.560 1.534 1.510 1.485 1.460 1.435 1.411 1.386 1.361 1.336 1.312 1.287 1.262 1.237 1.213 1.188 1.163 1.138 1.114 1.089 1.064 1.039 1.015 0.99 0.965 0.940 0.916 0.891 TYP VO 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.00 0.975 0.950 0.925 0.900 MAX 1% > VO 1.692 1.666 1.641 1.616 1.591 1.565 1.540 1.515 1.490 1.464 1.439 1.414 1.389 1.363 1.338 1.313 1.288 1.262 1.237 1.212 1.187 1.161 1.136 1.111 1.086 1.060 1.035 1.01 0.984 0.959 0.934 0.909 7
Pentium is a registered trademark of Intel Corporation
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
FUNCTIONAL DESCRIPTION
SUPPLY The chip is optimized to operate from a 3.3V + 5% rail but is also designed to work up to 6V maximum supply voltage. If VCC is out of the 3.3V + 5% voltage range, the quiescent current will increase somewhat and slight degradation of line regulation is expected. UNDER VOLTAGE LOCK-OUT CIRCUIT The under voltage lockout circuit consists of two comparators, the low battery and low VCC (low supply voltage) comparators. The output of the comparator gated with the Enable signal turns on or off the internal bias, enables or disables the CO output, and initiates or resets the soft start timers. POWER GOOD GENERATOR If the chip is enabled but not in UVLO condition, and the core voltage gets within +10% of the VID programmed value, then a high level Power Good signal is generated on the PWRGD pin to trigger the CPU power up sequence. If the chip is either disabled or enabled in UVLO condition, then PWRGD stays low. This condition is satisfied by the presence of an internal 100k pull-down resistor connected from PWRGD to ground. During soft start, PWRGD stays low independently from the status of Vcore voltage. During this time, PWRGD status is "don't care". BAND GAP REFERENCE A better than +1% precision band gap reference acts as the internal reference voltage standard of the chip, which all critical biasing voltages and currents are derived from. CORE CONVERTER CONTROLLER Precision VID DAC Reference The 5-bit digital to analog converter (DAC) serves as the programmable reference source of the core comparator. Programming is accomplished by CMOS logic level VID code applied to the DAC inputs. The VID code vs. the DAC output is shown in the Output Voltage Table. The accuracy of the VID DAC is maintained on the same level as the band gap reference. There is a 10A pull-up current on each DAC input while EN is high.
Core Comparator This is an ultra-fast hysteretic comparator with a typical propagation delay of approximately 20ns at a 20mV overdrive. Its hysteresis is determined by the resistance ratio of two external resistors, RHYS and ROH, and the high accuracy internal reference voltage, VREF. VHYS = ROH RHYS This chip can be used in standard hysteretic mode controller configuration and in DSPS (Dynamic Set Point Switching) hysteretic controller scheme. In standard hysteretic controller configuration, the core comparator compares the output voltage of the core converter, VCORE to the VID code programmed DAC voltage, VDAC. VCORE(t) = VDAC + VHYST(t) The core voltage ramps up and down between the two thresholds determined by the hysteresis of the comparator: VHCORE = VDAC + VHYST VLCORE = VDAC - VHYST In DSPS hysteretic controller configuration, the core comparator compares the core voltage, VCORE, not to the DAC voltage, VDAC directly but rather to a voltage less than the DAC voltage by a DSPS voltage, VDSPS.VCORE(t) = VDAC - VDSPS(t) + VHYST(t) The DSPS voltage is a function of the load current. It is generated from the current sense voltage, VCS , developed across a sense resistor, RCS, which is inserted in series with the main buck inductor and also used for current sensing for the cycle-by-cycle current limiting. The sense voltage is scaled up by the DSPS gain, ADSPS, which is set by the resistance ratio of two external resistors, RDAC and RCORE. VDSPS(t) = ADSPS * VCS(t) = (1 + RDAC RCORE ) * RCS * iCORE(t) VREF = 1.7V
Pentium is a registered trademark of Intel Corporation
8
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999 In DSPS hysteretic controller configuration (Cont'd) The comparator reference voltage positioning is such that an increasing current sense voltage, VCS, i,e, an elevating load current, causes the reference voltage to decrease, and as a consequence, the core output voltage also droops. At no load current, there is no droop while a maximum load, the droop is likewise maximum. In order for the core voltage to be positioned around the nominal VDAC voltage symmetrically and not just one way downward from the nominal value, a DSPS offset voltage, VDSPSOFFS, can be introduced. The offset voltage moves the comparator reference voltage upward at no load. At optimal offsetting, the reference voltage is above the nominal level for load currents less than half of the maximum load, and below the nominal value for currents higher than that. The maximum amount of core voltage positioning can be determined from the constrain which says the output voltage at no load condition must still remain below the upper threshold of the core voltage regulation window, and at maximum load, it must be above the lower threshold. The offset voltage can be generated across a resistor, ROH, which is also used to create the hysteresis voltage by forcing a unipolar DSPS offsetting current through it. The offsetting current is conveniently provided by a high value resistor, ROFFSET, connected from the comparator CMP pin to the ground.
V DSPSOFFS = R OH*IDSPS = R OH * VCS + VCORE R OH +R OFFSET R OH R OFFSET * V DAC
(R)
SC1406
Core Voltage Offsetting In order for the core voltage to be positioned around the nominal VDAC voltage symmetrically and not just always one direction downward, a core offset voltage, VOFFS can be introduced. The offset voltage moves the comparator reference voltage upwards. Using optimal offsetting, the core comparator reference voltage will be above the VID programmed nominal DAC voltage for load currents less than half of the maximum load, and below that for higher current. The maximum amount of the core voltage positioning can be determined from the constraint that the output voltage regulation window, and at maximum load, it has to be above the lower threshold. The positioning offset voltage can be generated across the same resistor, ROH also used to create the hysteresis voltage, by forcing a unipolar offsetting current through it. The offsetting current is conveniently provided by a high value resistor, ROFFS connected from the comparator CMP pin to the ground. Current Limit Comparator The current limit comparator monitors the core converter output current and turns the high side switch off when the current exceeds the upper current limit threshold, VHCL and re-enable only if the load current drops below the lower current limit threshold, VLCL. The current is sensed by monitoring the voltage drop across the current sense resistor, RCS, connected in series with the core converter main inductor (the same resistor used for DSPS input signal generation). The thresholds have the following relationships:
VHCL = 3 * VLCL = 2 * VHYSCL = R CLOH * V REF R CLSET R CLOH * V REF R CLSET
VCS << VCORE , VCORE = VDAC ,ROH << ROFFSET
In DSPS hysterestic controller configuration, the comparator thresholds can be calculated from the DAC voltage, VDAC, the DSPS offsetting voltage, VDSPSOFFS, the DSPS voltage VDSPS, and the bipolar hysteresis voltage, VHYST by summing them at the comparator inputs at the appropriate load current levels:
Vcore := Vdac * (Roffset + Roh ) * Rcore - Rcs * Icore * Roffset * (Rcore + Rdac Rcore * Roffset - Rdac * Roh
R CLOH * V REF R CLSET
Vcore := 2 * Vhys *
Rcore * (Roffset + Roh ) * Rcore * Roffset - Rdac * Roh Re sr +
Re sr Rcore * (Roffset + Roh ) Rcore * Roffset - Rdac * Roh
Pentium is a registered trademark of Intel Corporation
9
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999 Core Converter Soft Start Timer The main purpose of this block is to control the rampup time of the core voltage in order to reduce the initial inrush current on the core input voltage (battery) rail. The soft start circuit consists of an internal current source, external soft start timing capacitor, internal switch across the capacitor, and a comparator monitoring the capacitor voltage. LINEAR REGULATOR CONTROLLER 1.5V Linear Regulator This block is a linear regulator controller, which drives an external PNP bipolar transistor as a pass element. The linear regulator is capable of delivering 500mA steady state DC current and should support transient current of 1A, assuming the output filtering capacitor is properly selected to provide enough charge for the duration of the load transient. 2.5V Linear Regulator This block is a low drop-out (LDO) linear regulator controller, which drives an external PNP bipolar transistor as a pass element. The LDO linear regulator is capable of delivering 100mA steady DC current and should support transient current of 100mA, assuming the output filtering capacitor is properly selected to provide enough charge for the duration of the load transient.
(R)
SC1406
Linear Regulator Soft Start Timer A soft start timer circuit of the linear regulators is similar to that of the core converter, and is used to control the ramp up time of the linear regulator output voltages. For maximum flexibility in controlling the start up sequence, the soft start function of the linear regulators is separated from that of the core converter. VOLTAGE CLAMP The level translator converts an input voltage swing on the IO rail, into a voltage swing on the CLK or VCC rail depending on where the open drain output of the translator is tied to through an external pull-up resistor. The level translator has to track the input in phase, and must be able to switch in 5ns (typical) following an input threshold intercept.
APPLICATION INFORMATION
Power on/off Sequence
Pentium is a registered trademark of Intel Corporation
10
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320
PORTABLE PENTIUM II & III POWER SUPPLY CONTROLLER
PRELIMINARY - August 27, 1999
(R)
SC1406
OUTLINE DRAWING - TSSOP-28
Pentium is a registered trademark of Intel Corporation
11
(c) 1999 SEMTECH CORP.
652 MITCHELL ROAD
NEWBURY PARK CA 91320

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